Method for embedding silicon die into a stacked package

ABSTRACT

Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment, the configuration includes a substrate with a recess, a first die carried by the substrate wherein the die substantially covers the recess, and a logic component carried by the die in a location exposed by the recess. The logic component can be substantially coplanar with the substrate. The die is electrically connected to a terminal on a one side of the substrate, and the logic component is electrically connected to a terminal on an opposite side of the substrate.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No. 15/648,026 filed Jul. 12, 2017, which is a divisional of U.S. application Ser. No. 12/400,632 filed Mar. 9, 2009, now U.S. Pat. No. 9,735,136, which are incorporated herein by reference in their entirety.

TECHNICAL FIELD

The present disclosure is related to microelectronic devices with logic components and associated methods of manufacturing.

BACKGROUND

Microelectronic dies are typically manufactured on semiconductor wafers or other types of workpieces using sophisticated equipment and processes. The individual dies generally include a plurality of bond-pads coupled to integrated circuits. The bond-pads provide external contacts through which data signals, supply voltage, and other electrical signals are transmitted to and from the integrated circuits. Demand for these components requires ever higher performance and smaller packaging. To meet this demand, it has become common practice to stack dies to achieve more memory or computing power in the same unit of space or footprint. This technique reduces the footprint of the devices but increases the height of the package. The same demand for small, powerful devices limits the effectiveness of this technique beyond a certain height threshold depending on the device and its use. Another adverse effect of taller die packages is the increased latency caused by the necessarily longer wirebonds between the upper die(s) and the lead frame or interposer substrate.

Most current packaged devices have a logic component that adds functionality not found in earlier microelectronic packages. However, adding a logic component to a stack of dies adds another die that further increases the height of the die stack. FIG. 1 depicts a device 100 with an interposer substrate 104, a first die 106 a attached to the interposer substrate 104, and a second die 106 b stacked on the first die 106 a. The dies 106 a-b are electrically connected to the substrate 104 by wirebonds 108 that extend between bond pads 112 on the substrate 104 and bond pads 113 on the dies 106 a-b. The device 100 also has a logic component 114 on top of the second die 106 b that is electrically connected to the substrate 104 by additional wirebonds 116. As more dies and other layers are stacked onto each other the distance increases between the substrate 104 and both the upper die (e.g., die 106 b) and the logic component 114. This increases both the length of the wirebonds 108 and 116, which also increases the latency in the electrical signals and the height of the die stack. Both the height of the device 100 and the length of the wirebonds 108 and 116 affect the performance and viability of devices.

FIG. 2 illustrates another existing device 200 with a substrate 202 and multiple dies 204 stacked on the substrate 202. The dies 204 have through silicon vias (“TSVs”) 206 that interconnect the dies 204 to each other and to the substrate 202, and a logic component 208 is attached to the bottom of the substrate 202 and electrically coupled to the dies 204 and substrate 202 by interlayer wiring 210. The TSVs mitigate latency problems in large die stacks, but TSVs are more expensive than wirebonds. In light of the existing devices 100 and 200, there is a need for cost-effective structural arrangements that can reduce both the latency and overall size of microelectronic device packages.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partially schematic cross-sectional view of a microelectronic device in accordance with the prior art.

FIG. 2 is a partially schematic cross-sectional view of a microelectronic device in accordance with the prior art.

FIG. 3 is a partially schematic cross-sectional view of a microelectronic device in accordance with an embodiment of the new technology.

FIG. 4 is a partially schematic cross-sectional view of a microelectronic device in accordance with another embodiment of the new technology.

FIG. 5 is a partially schematic cross-sectional view of a microelectronic device in accordance with a further embodiment of the new technology.

FIG. 6 is a schematic diagram of a system that includes one or more microelectronic device packages in accordance with embodiments of the new technology.

DETAILED DESCRIPTION

Specific details of several embodiments of the new technology are described below with reference to microelectronic device configurations with logic components and associated methods of manufacturing. Typical microelectronic device packages include microelectronic circuitry or components, thin-film recording heads, data storage elements, micro fluidic devices, and other components manufactured on microelectronic substrates. Micromachines and micromechanical devices are included within this definition because they are manufactured using technology similar to that used in the fabrication of integrated circuits. The term “microfeature substrate” or “die” is used throughout to include semiconductor substrates and other types of substrates upon which and/or in which semiconductor devices, other types of microelectronic devices, micromechanical devices, data storage elements, read/write components, and other features are fabricated. Suitable materials for dies can include semiconductor pieces (e.g., doped silicon wafers or gallium arsenide wafers), non-conductive pieces (e.g., various ceramic substrates), or conductive pieces. Microfeature dies can also include one or more layers (e.g., conductive, semiconductive, and/or dielectric) that are situated upon and/or within one another. These layers can include or form a wide variety of electrical components, mechanical components, and/or systems of such components (e.g., integrated circuits, memory devices, processors, imagers, micromechanical systems, etc.). The term “surface” can encompass planar and nonplanar surfaces of a semiconductor substrate with or without patterned and non-patterned features. A person skilled in the relevant art will also understand that the new technology may have additional embodiments, and that the new technology may be practiced without several of the details of the embodiments described below with references to FIGS. 3-6.

In several embodiments of the new technology, the microelectronic device comprises an interposer substrate with first bond pads on a first side of the interposer substrate, wherein the interposer substrate is formed with a recess extending from the first side to the second side. The microelectronic device also includes a die stack comprising a plurality of dies in a stack, wherein a base die is attached to the first side of the interposer substrate such that at least a portion of a surface of the base die is exposed by the recess. A logic component is attached to the surface of the base die exposed through the recess such that the logic component is positioned at least substantially between the first side of the interposer substrate and the second side of the interposer substrate.

FIG. 3 is a partially schematic cross-sectional view of a microelectronic device 300 with multiple dies 318 and a logic component 316 in a stacked arrangement according to one embodiment of the new technology. As shown in FIG. 3, the microelectronic device 300 can have an interposer substrate 302 including a first side 312 a, a second side 312 b, ball pads 304, first bond pads 306 at the first side 312 a, and second bond pads 314 at the second side 312 b. The interposer substrate 302 can also include printed circuitry 308 that electrically connects the ball pads 304 to corresponding first bond pads 306, and wiring 310 that electrically connects the ball pads 304 to corresponding second bond pads 314. The wiring 310 is formed using processes for manufacturing printed circuit boards. The ball pads 304 provide electrical communication between the microelectronic device 300 and other electrical contacts of a larger printed circuit board to which the microelectronic device 300 is attached. The interposer substrate 302 shown in FIG. 3 further includes a recess 324, such as a slot or other opening through the interposer substrate 302, which can be located between the first bond pads 306.

The dies 318 can include a base die 318 a attached to the second side 312 b of the interposer substrate 302 using an adhesive tape, adhesive paste or another suitable attachment mechanism. Additional dies 318 can be stacked on the base die 318 a. The dies 318 can be made of silicon or any other suitable material, and can be a memory device (e.g., DRAM) or other electronic and/or mechanical component (e.g., a NAND stack). Although FIG. 3 shows three dies 318, a person of ordinary skill in the art will appreciate that the number of dies 318 depends on the application and requirements of the device. The dies 318 can be separated by spacers 320 positioned between adjacent dies 318 so that wirebonds 322 can be attached to die bond pads 317 on individual dies 318. The spacers 320 can be blank silicon chips, tape, or other suitable items. In another application, a spacer is placed between only selected dies, or in other applications all of the dies 318 can be attached directly to one another without being separated by spacers. The type, layout, and spacing of the spacers 320 can be determined according to the requirements of a given application. For example, the height of the stack of dies 318 and spacers 320 can affect the time it takes electrical signals to pass along the wirebonds 322 (i.e., the latency). In general, and all other things being equal, shorter wirebonds provide a faster response and lower latency than longer wirebonds. Thus, the length of the wirebonds 322 for the upper dies in tall die stacks is an important factor in providing the desired latency and concomitant performance.

The logic component 316 can be located in the recess 324 through the interposer substrate 302. In this embodiment, the logic component 316 is attached to the base die 318 a which is adjacent the second side 312 b of the interposer substrate 302. This embodiment of the microelectronic device 300 reduces the stack height and latency compared to the device shown in FIG. 1 because the placement of the logic component 316 in recess the 324 does not increase the height of the device 300. Additionally, the wirebonds 328 for the logic component 316 can pass through the recess 324 to electrically connect the logic component 316 to the first bonds pads 306. The recess 324 can be formed in any shape, size, and location that can contain the logic component 316 and the wirebonds 328. As a result, the embodiment of the microelectronic device 300 shown in FIG. 3 provides a compact arrangement that can fit into small enclosures and use short wirebonds 328 for the logic component 316.

In several other embodiments of the new technology, the microelectronic device comprises an interposer substrate having a first side and a second side, and a recess open at the second side. The recess can be a through hole passing completely through the interposer substrate, or the recess can be a blind hole extending a distance into the interposer substrate without penetrating the opposing side of the substrate. The microelectronic device also includes a plurality of second terminals at the second side. One or more individual dies are attached to the first side of the interposer substrate, and the dies include integrated circuitry and bond sites electrically connected to the first terminals of the interposer substrate. A logic component can be positioned in the recess of the interposer substrate, located between the first side and second side of the interposer substrate, and electrically connected to the second terminals at the second side.

Several embodiments of methods for assembling a microelectronic device package comprises forming an interposer substrate with a recess, and attaching a die structure to a one side of the interposer substrate. The recess can be a blind hole or a through hole. The method continues by attaching a logic component to the microelectronic device package such that at least a portion of the logic component is positioned between the one side of the interposer substrate and an opposite side of the interposer substrate, and such that at least a portion of the logic component is accessible through the recess on the opposite side. The method also includes electrically connecting the die structure and the logic component to bond pads on the interposer substrate.

FIG. 4 is a partially schematic cross-sectional view of an embodiment of another microelectronic device 400, and like reference numbers refer to like components in FIGS. 3 and 4. In this embodiment, the microelectronic device 400 includes the interposer substrate 302, a die stack 410 having one or more dies 412 and a logic component 414, and through-silicon-vias (TSVs) 416. One of the dies is a base die 412 a attached to the second side 312 b of the interposer substrate 302. The TSVs 416 electrically couple the dies 412 to each other and/or the interposer substrate 302 to transmit the electrical signals and voltages to/from the dies 412.

The logic component 414 is attached to the base die 412 a. The logic component 414 is positioned in the recess 324 and electrically connected to the second bond pads 306 by wirebonds 328. This configuration enables a shorter overall package compared to conventional designs because the logic component 414 is located in the recess 324 instead of on top of the die stack 410. In addition, the short wirebonds 328 to the logic component 414 have a low latency. Thus, the device 400 according to this embodiment achieves good performance from a small device.

FIG. 5 is a partially schematic cross-sectional view of a microelectronic device 500 in accordance with a further embodiment of the new technology. The device 500 includes an interposer substrate 502 having a first side 506 a, a second side 506 b, and a recess defined by a blind hole 504 extending from the first side 506 a of the interposer substrate 502 to an intermediate depth within the interposer substrate 502. The blind hole 504 does not extend completely through to the second side 506 b of the substrate 502. The depth of the blind hole 504 depends upon the design constraints and preferences of a given application, and can extend through the substrate 502 a greater or lesser distance than what is shown in FIG. 5. It is understood by a person of ordinary skill in the art that previous embodiments discussed above with reference to FIGS. 3 and 4, which include an opening passing completely through a substrate, can alternatively include a blind hole similar to the blind hole 504 discussed with reference to FIG. 5. Accordingly, the various configurations and features previously discussed can be implemented with a blind hole or a through hole without departing from the scope of the present disclosure.

The microelectronic device 500 further includes a logic component 520 positioned in the blind hole 504 and attached to the interposer substrate 502. The dimensions of the blind hole 504 can vary both in depth and width to accommodate logic components of varying sizes. For example, the blind hole 504 can be sized according to the size of the logic component 520 such that the logic component 520 is substantially flush with the first side 506 a of the substrate 502, but in other examples a portion of the logic component can extend below the first side 506 a of the substrate 502 by a distance that is less than the distance a solder ball 508 or other connector projects away from a ball pad 509. The logic component 520 is electrically connected to bond pads 507 a by wirebonds 522.

The microelectronic device can also include one or more dies 530 stacked on the second side 506 b of the substrate and connected to bond pads 507 b by wire bonds 532. As described above, the dies 530 can include any number, type, and configuration of dies depending on the application of the device 500. This configuration provides a short, compact microelectronic device design because the logic component 520 is positioned, at least in part, between the first side 506 a and the second side 506 b of the interposer substrate 502. Also, the length of the wirebonds is reduced, which correspondingly reduces the latency of the device 500.

Individual microelectronic device packages may be incorporated into myriad larger and/or more complex systems. A representative system 600 is shown schematically in FIG. 6. The system 600 can include a processor 601, a memory 602, input/output devices 603, and/or other subsystems or components 604. The resulting system 600 can perform a wide variety of computing, processing, storage, sensor, and/or other functions. Accordingly, the representative system 600 can include, without limitation, computers and/or other data processors, for example, desktop computers, laptop computers, Internet appliances, and hand-held devices (e.g., palm-top computers, wearable computers, cellular or mobile phones, multi-processor systems, processor-based or programmable consumer electronics, network computers, mini computers). The representative system 600 can also include servers and associated server subsystems, display devices, and/or memory devices. Components of the system 600 may be housed in a single unit or distributed over multiple, interconnected units, e.g., through a communications network. Components can accordingly include local and/or remote memory storage devices and any of a wide variety of computer-readable media, including magnetic or optically readable or removable computer disks.

From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but well-known structures and functions have not been shown or described in detail to avoid unnecessarily obscuring the description of the embodiments of the invention. Where the context permits, singular or plural terms may also include the plural or singular term, respectively. Unless the word “or” is associated with an express clause indicating that the word should be limited to mean only a single item exclusive from the other items in reference to a list of two or more items, then the use of “or” in such a list shall be interpreted as including (a) any single item in the list, (b) all of the items in the list, or (c) any combination of the items in the list.

From the foregoing, it will be appreciated that specific embodiments described above are for purposes of illustration and that various modifications may be made without deviating from the invention. Aspects of the disclosure described in the context of particular embodiments may be combined or eliminated in other embodiments. Further, while advantages associated with certain embodiments of the disclosure may have been described in the context of those embodiments, other embodiments may also exhibit such advantages, but not all embodiments need necessarily exhibit such advantages to fall within the scope of the disclosure. Accordingly, the present invention is not limited to the embodiments described above, which were provided for ease of understanding, but rather the invention includes any and all other embodiments defined by the claims. 

I/We claim:
 1. A semiconductor device package, comprising: an interposer substrate with an opening extending through the interposer substrate from a first outer surface to a second outer surface; a first semiconductor die attached to the first outer surface of the interposer substrate over the opening; a second semiconductor die attached to the first semiconductor die and disposed at least partially within the opening; and wire bonds electrically connecting the second semiconductor die to bond pads on the second outer surface of the interposer substrate.
 2. The semiconductor device package of claim 1 further comprising a third semiconductor die attached to the first semiconductor die opposite the first outer surface.
 3. The semiconductor device package of claim 2, wherein the third semiconductor die is electrically coupled to the second semiconductor die by one or more interconnects.
 4. The semiconductor device package of claim 3, wherein the one or more interconnects comprise wirebonds and/or through-silicon vias.
 5. The semiconductor device package of claim 2 wherein the third semiconductor die is separated from the semiconductor die by a spacer.
 6. The semiconductor device package of claim 1, wherein the first semiconductor die completely overlaps the opening.
 7. The semiconductor device package of claim 1, wherein the opening is centrally located on the interposer substrate.
 8. The semiconductor device package of claim 1, wherein the first semiconductor die comprises a NAND memory die and wherein the second semiconductor die comprises a controller.
 9. The semiconductor device package of claim 1, wherein the second semiconductor die has a third outer surface opposite the first semiconductor die and wherein the third outer surface is flush with the second outer surface.
 10. The semiconductor device package of claim 1, wherein a portion of the second semiconductor die projects outside of the opening and beyond the interposer substrate.
 11. The semiconductor device package of claim 1, wherein the opening has a first planform area and wherein the second semiconductor die has a second planform area substantially the same as the first planform area.
 12. A semiconductor device package, comprising: an interposer substrate with an opening extending through the interposer substrate from a first outer surface to a second outer surface; a stack of memory dies attached to the first outer surface of the interposer substrate over the opening; a controller die attached to the stack of memory dies and disposed at least partially within the opening; and wire bonds electrically connecting the controller die to bond pads on the second outer surface of the interposer substrate.
 13. The semiconductor device package of claim 12, wherein the stack of memory die are electrically coupled to one another and to the interposer substrate by one or more interconnects.
 14. The semiconductor device package of claim 13, wherein the one or more interconnects comprise wire bonds or through-silicon vias (TSVs).
 15. The semiconductor device package of claim 12, wherein the opening has a first planform area and wherein the controller die has a second planform area substantially the same as the first planform area.
 16. The semiconductor device package of claim 12, wherein the stack of memory dies completely overlaps the opening.
 17. The semiconductor device package of claim 12, wherein the opening is centrally located on the interposer substrate.
 18. The semiconductor device package of claim 12, wherein the controller die has a third outer surface opposite the stack of memory dies and wherein the third outer surface is flush with the second outer surface.
 19. The semiconductor device package of claim 12, wherein a portion of the controller die projects outside of the opening and beyond the interposer substrate.
 20. A semiconductor device package, comprising: an interposer substrate with an opening extending through the interposer substrate from a first outer surface to a second outer surface; a stack of memory dies disposed over the opening and having a lower surface attached to the first outer surface of the interposer substrate along a periphery of the opening; a controller die attached to the lower surface of the stack of memory dies and disposed at least partially within the opening; and wire bonds electrically connecting the controller die to bond pads on the second outer surface of the interposer substrate. 